Michael A. Hicks
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Title: Towards Scalable I/O on a Many-core Architecture
Author(s): Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope
Publication Date: July 2010
Publication Type: Conference
Book Title: International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS)
Publisher: IEEE
Location: London
Abstract: The limitations of conventional processor performance scaling mean that general purpose many-core processors are increasingly becoming a reality. Conventional hardware device I/O, interrupt handling and operating system stacks scale poorly and are inefficient when compared with the parallelism that these architectures provide. Many-core I/O requires a decentralised approach where not every core is directly connected to the I/O infrastructure. As such, this paper discusses a software and hardware model designed to take full advantage of I/O parallelism in the Self-adaptive Virtual Processor (SVP) concurrency model and the Microgrid many-core architecture.

The generic software I/O stack presented describes a high-level method by which clients and I/O resources can communicate and synchronise in a parallel and decentralised environment. The associated hardware implementation provides a facility to the higher-level interface through the introduction of specialised emph{I/O Cores} which provide high-speed communication between external devices directly and the on-chip memory system.

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